1. Field of the Invention
The present invention relates to exception logic for handling floating point exceptions, and more particularly, to a system for qualifying register file write enables using self-timed floating point exception flags from a floating point processing unit.
2. Description of the Prior Art
Recently, floating point processors have been designed which allow concurrent execution of a floating point multiply, divide, add and load or store instructions, thereby significantly increasing the processing efficiency of a floating point processor. For example, DeLano et al. describe in an article entitled "A High Speed Superscalar PA-RISC Processor", Proceedings of the Compcon Spring 1992, Digest of Papers, San Francisco, Calif., Feb. 24-28, 1992, a central processing unit comprising an integer processor and a floating point coprocessor which achieves exceptional performance and structural density. The floating point coprocessor consists of a register file, a floating point ALU, a floating point multiplier, and a floating point divide/square root unit and is integrated onto the same chip as the integer processor. Dynamic logic was used to exploit the speed and density characteristics of such circuits using a system of self-timed logic.
The handling of floating point exceptions has been found to be a critical timing path in floating point coprocessors of the type described by DeLano et al. For example, when an instruction causes a trap due to a floating point exception, the contents of the original operand registers and the contents of the destination registers must be preserved so that the trap (or exception) handler can properly process the exception. However, in order to avoid disturbing the contents of the destination register, the destination register cannot be written until after it is known that the floating point operation did not trap. Because floating point exceptions such as overflow, underflow and inexact are based on the rounding of the result, the exception flags cannot be calculated before the result. As a result, the results and the exception flags typically become valid during the same phase. Unfortunately, previous floating point processors have not taken advantage of this characteristic to write the register file in the same phase that the results become valid. Instead, a control line driver has been set up so that the register file is written during the next phase of the clock. This has typically been done to account for static hazards or glitches in the exception flag signals which may carry through to cause glitches in the register file write signals.
Unfortunately, by delaying the write of the result to the register file by a phase, additional latency is added to the floating point operations. In order to prevent this additional latency from impacting floating point performance, an extra level of bypass has typically been required so that the result of the floating point operation which is being written to the register file can be used as an operand without going through the register file. This adds substantial area and complexity to the control design and is generally undesirable.
Accordingly, in order to provide a floating point data path with minimal latency, it is desired to write the destination register during the same phase in which the result of the floating point operation becomes valid. However, in order to do this, the write enable to the register file must be glitch-free (i.e., static hazards must be removed from the write enable signal). In other words, the write enable must be provided to the register file if and only if there are no exceptions and the destination register is to be written. The write enable may not be allowed to glitch true and then return to false in the event of an exception. The present invention has been designed to meet these needs.